1. Technical Field
The invention relates to a reference potential generating circuit of a semiconductor memory and more particularly, to a reference potential generating circuit included in an internal power supply circuit mounted in a semiconductor memory.
2. Related Art
In the related art, various technology for suppressing overshoot at the time of supplying power in a voltage generating circuit mounted in a semiconductor integrated circuit have been suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2005-122574).
FIG. 11 illustrates an example of a reference potential generating circuit included in an internal power supply circuit mounted in a ROM functioning as a semiconductor memory.
A reference potential generating circuit 100 illustrated in FIG. 11 has a structure in which a PMOS transistor P2 and an NMOS transistor N3 for reference potential correction are connected in series and this circuit is connected parallel to a circuit in which a PMOS transistor P1, plural DMOS transistors D1 to D4, an NMOS transistor N1 and an NMOS transistor N2 are connected in series. The gate of the PMOS transistor P1 receives an internal power supply enable signal CEB_GEN output by an internal power supply control circuit (not illustrated). The plural DMOS transistors D1 to D4 are for current supply and whose gates are connected to each other. The NMOS transistor N1 is for temperature compensation and whose gate is connected to the gates of the DMOS transistors D1 to D4. The gate of NMOS transistor N2 is applied with a power supply voltage VCC. A reference potential VCWREF is output from a connection point C of the DMOS transistors D2 and D3.
In the reference potential generating circuit 100 having the above configuration, since a variation in the reference potential VCWREF is fed back by the NMOS transistor N1 for temperature compensation, excellent temperature and voltage characteristics may be obtained.
A gate of the PMOS transistor P2 for voltage correction is connected to a connection point B of the DMOS transistor D4 and the NMOS transistor N1, and the power supply voltage VCC is applied to a gate of the NMOS transistor N3.
For example, when the internal power supply enable signal CEB_GEN is at a low level, a mode becomes a normal operation mode. When the internal power supply enable signal CEB_GEN is at a high level, the mode becomes a standby mode.
In the reference potential generating circuit 100, when a level of the internal power supply enable signal CEB_GEN becomes low and the mode becomes the normal operation mode, in order to start to supply power to an internal circuit by the internal power supply circuit, first, if the PMOS transistor P1 is turned on, a current Ia flows through the DMOS transistor D1 and a current Id flows through the DMOS transistor D4. Thereby, as illustrated in FIG. 12, a voltage VREF_A at a connection point A gradually increases. However, a coupling noise of the voltage VREF_A with respect to a voltage VPG at the connection point B increases, and the voltage VPG increases as the voltage VREF_A increases. As a result, the PMOS transistor P2 for reference potential correction is not turned on and the current Ip does not flow.
Meanwhile, since the current Ia immediately flows through the DMOS transistors D1 to D4 for current supply, the reference potential VCWREF output from the connection point C may overshoot, as illustrated in FIG. 12. This phenomenon becomes notable when resistance generated from the gate of the PMOS transistor P2 for reference potential correction to a ground through the NMOS transistors N1 and N2 for temperature compensation increases.